Electron-beam-addressed active-matrix spatial light modulator

ABSTRACT

A spatial light modulator contains a substrate ( 90 ), a plurality of overlying liquid-crystal cells ( 202 ), a plurality of respectively corresponding transistors ( 204 ), an electron-beam system ( 400  and  500 ), and a control component ( 203 ). Each transistor is in electrical communication with the corresponding liquid-crystal cell. The electron-beam system bombards each transistor with electrons that cause it to be selectively in (i) a non-conductive condition in which its channel-region electric field is substantially insufficient for conduction or (ii) a conductive condition in which its channel-region electric field is sufficient for at least partial conduction. During selected time periods when a transistor is in its conductive condition, the control component provides the transistor with a control signal that results in the polarization direction of specified light being selectively rotated in passing through the corresponding liquid-crystal cell.

CROSS-REFERENCE TO RELATED APPLICATION

[0001] This application claims the priority of, and hereby incorporatesby reference, U.S. provisional patent application 60/457,444, filed 26Mar. 2003.

FIELD OF USE

[0002] This invention relates to image presentation and, moreparticularly, to liquid-crystal image presentation technology.

BACKGROUND OF THE INVENTION

[0003] As computer-generated image technology becomes more realistic,the need for projection display systems capable of reproducing imageswith high fidelity becomes critical. High-fidelity projection displaysystems are needed in electronic entertainment applications, and areessential in simulation and training where the perceived reality of theenvironment is central to the purpose of the simulation and training.

[0004] An essential feature of image fidelity is the property of imageresolution. It is desirable for the spatial resolution of the display tobe higher than the resolution of the addressing means so that imagequality is not degraded by aliasing artifacts.

[0005] Another essential feature of image fidelity is the isolation ofimage information to the intended area, region, or display elementsaddressed by the addressing means. Capacitive coupling between, andresistive losses in, array bus electrodes conducting electrical signalsfrom the addressing means to the display elements is a contributingfactor to degradation of image fidelity by unintended transference ofimage information between the display elements.

[0006] In the case of a liquid-crystal display, another essentialrequirement for image fidelity is the maintenance of good color and grayscale by controlling thickness variations in the liquid-crystal film.

RELATED ART

[0007] From the early 1950s through the late 1960s, there were a numberof attempts to create spatial light modulators addressed by electronbeams. This was a natural evolution of the CRT, the major direct-viewtechnology of the time. The first commercially successful projectionproduct that employed electron-beam addressing was the Eidophorlight-valve projector, a large continuously pumped system in which theelectron beam created a pattern of electric charge in a dielectric oilfilm. The charge pattern caused a deformation pattern in the oil filmwhereby the amplitude of the deformation was proportional to themagnitude of the local electric charge. Light from a (xenon) lamp wasreflected from the oil film and evaluated by a Schlieren optical system.The magnitude of light passing the Schlieren stop in the optical system,and projected onto a viewing screen, was proportional to the magnitudeof the deformation pattern in the oil film.

[0008] This same fundamental strategy of using charges deposited on adielectric to modulate a deformable medium was commercially successfulin the General ElectricTalaria product line of oil-film light-valveprojectors. The Talaria projector was a more portable, less expensive,transmissive version of the Eidophor projector, but still requiredcontinuous vacuum pumping because the oil film was exposed to both theelectron beam and vacuum. The performance of the Eidophor and Talarialight-valve oil-film projection systems was satisfactory but, even withcontinuous exhaust, the maintenance and operating cost of the systemswas high.

[0009] Except for the problems associated with direct oil-filmaddressing, the oil-film light-valve concept was sufficiently attractivethat several development efforts were initiated to isolate the(electron-beam) addressing means from the modulation means. The logicalextension of the oil-film projection system was the substitution of thedirectly written oil film by an electron-beam target in which a matrixof conductive pins, isolated from each other, served as the faceplate ofthe vacuum tube. An oil film on the non-vacuum side of the pin-matrixfaceplate was locally deformed in response to electric charge depositedby an electron beam on the vacuum side of the pin matrix. Lightreflected from the oil film was analyzed by an apertured mirror. Theresultant deformation pattern was projected onto a viewing screen.

[0010] A variation of the pin-matrix system contained a multilayerdielectric mirror suspended over the non-vacuum side of a pin-matrixfaceplate. The mirror was deformed at the conductive pins in response tocharge deposited by an electron beam. This device functioned opticallyin a manner similar to that employed in the currently commerciallysuccessful Texas Instruments DLP projectors. U.S. Pat. Nos. 5,287,215and 5,471,314 describe a more modern embodiment of this concept.

[0011] The preceding projection systems demonstrated the concept oftransferring charge from an addressing means to a modulating means byuse of an array of conducting pins in an electrically non-conductivesubstrate. However, the construction methods and substrate materialsfundamentally limited the display resolution. Additionally, anunfavorable aspect ratio resulting from the large substrate thicknesscompared to the diameter of the feedthrough pins generated capacitivecrosstalk between pins. This further reduced display resolution.

[0012] An electron-beam-addressed liquid-crystal display developed byTektronix utilized electron-beam-induced secondary electron emissionfrom a dielectric surface to produce a localized positive charge on athin dielectric membrane that separated a liquid-crystal film from thevacuum environment. The liquid-crystal film was divided into an array ofliquid-crystal cells. Responding to the electric field induced by thedeposited charge, the liquid-crystal cells modulated polarized light tocreate a projected image. The charge pattern created by a “writing”electron beam remained on the dielectric membrane until removed by an“erase” electron beam.

[0013] The Tektronix display successfully demonstrated the basic conceptof creating an electric field by means of charge deposited on adielectric by an electron beam, as well as the mechanism for chargedeposition and removal. However, the deposited charge was, necessarily,monopolar. This resulted in unwanted residual DC voltage on the liquidcrystal. Commercialization opportunities for the Tektronix display werealso limited by the difficulty involved with fabrication of theliquid-crystal cells in a high-vacuum environment.

[0014] In each case of recent prior art, where the addressing techniqueutilizes charge deposition by an electron beam and where the displaytechnique employs liquid-crystal modulation resulting from the depositedcharge, the mechanism used to transfer information (electrical signals)from the electron-beam target to the display electrodes of the liquidcrystal cells has fundamentally limited the resolution of the display.Additionally, the liquid crystal must be isolated from the vacuumenvironment required for generation of the electron beam.

[0015] In a conventional active-matrix liquid-crystal display (“AMLCD”),each pixel contains a thin-film transistor (“TFT”), effectively allowingan unlimited number of pixels to be addressed for image presentation.Each TFT is a three-terminal field-effect device typically formed on aglass or silicon substrate. The TFTs are switched on and off by voltagesapplied through the (horizontal) scan lines of the array to the TFTgates. The source of each TFT is electrically connected to one of agroup of display electrodes and is capacitively coupled through a pixelliquid-crystal cell to a common ground electrode.

[0016] The ground electrode is typically formed on a sheet of glassspaced apart from the display electrodes by means of spacer elementsdisposed between the ground electrode, on one hand, and the displayelectrodes, on the other hand. Precise control of the electrode spacingis necessary in order to accurately reproduce the character of the inputimage. Variations in the spacing distance produce optical pathdifferences, leading to non-uniform image gray level and correspondingloss in image quality. The electrode spacing is controlled bydimensional tolerance of the spacing elements and the degree to whichthe ground and TFT substrates conform to the spacing elements. Althoughflexibility of the substrates enhances conformal properties, a lack offlatness when the modulator is used in reflective mode can result inreflected image distortion.

[0017] Each row in the active matrix is scanned sequentially during avideo field. During the time interval when an activation voltage isapplied to the gates of all the TFTs in a particular row, datainformation is applied to each TFT drain (column) electrode in order tocharge the associated pixel liquid-crystal cell to a voltage consistentwith the gray level of the applied picture information. A driver isrequired for each row and column. On alternate video fields, thepolarity of the data information is inverted, thereby preventing DCoffset across the liquid-crystal material.

[0018] Each TFT has a low conductance in the off state. This preventsthe associated cell capacitor from discharging during the video frame. Arow addressed in one frame thus typically remain activated well into thesubsequent frame. The overlapping row activation, as well as thetypically slow optical response of liquid-crystal material, createsundesirable artifacts in time-varying images.

[0019] Additionally, image information is conducted to each TFT in thepixel array by way of bus electrodes that transmit electrical signalsfrom the row and column drivers. These bus electrodes degrade imagequality due to resistive losses in each bus electrode between its driverand its pixel TFTs and due to capacitive coupling between each buselectrode and other pixel TFTs in proximity to that bus electrode. Ofparticular importance are the parasitic capacitance between the gates ofthe TFTs, on one hand, and their source electrodes, on the other hand.These parasitic capacitances reduce the spatial resolution inconventional AMLCDs because, as the pixel TFTs become smaller, the fixedparasitic capacitances become a larger fraction of the total pixelcapacitances.

[0020] A need exists for an active matrix light modulator whose spatialresolution is not limited by the parasitic impedance of the addressingelectrodes. It is desirable for such a spatial light modulator to avoidundesirable time-varying image artifacts. It is also desirable for themodulator to employ liquid-crystal technology with the spacing andflatness required for image projection without loss of fidelity.

GENERAL DISCLOSURE OF THE INVENTION

[0021] An active-matrix light modulator in accordance with the inventioncontains a substrate, a plurality of liquid-crystal cells overlying thesubstrate, an active matrix formed with a plurality of transistorsrespectively corresponding to the liquid-crystal cells, an electron-beamsystem, and a control component. Each transistor is in electricalcommunication with the corresponding liquid-crystal cell.

[0022] The electron-beam system bombards the transistors with electronsthat cause each transistor to be selectively in (i) a non-conductivecondition in which that transistor's channel-region electric field issubstantially insufficient for conduction or (ii) a conductive conditionin which that transistor's channel-region electric field is sufficientfor at least partial conduction. Since “conductive condition” is definedhere for a transistor with reference to its channel-region electricfield, a transistor can be in its conductive condition even though thetransistor is not actually conducting current. For instance, one of thecurrent-carrying terminals of a transistor whose channel-region electricfield is sufficient to place the transistor in its conductive conditionmay receive a signal at a high, effectively infinite, impedance so thatsubstantially no current flows through the transistor. Such a transistoris thus disabled.

[0023] The liquid-crystal cells overlie the substrate where it issubstantially transmissive of specified light which passes through thecells. The specified light, typically visible light such as color light,is polarized and is characterized by a polarization direction that canrotate as the light passes through each liquid-crystal cell. Duringselected time periods when a transistor is in its conductive conditionand not disabled, the control component provides that transistor with acontrol signal that results in the specified light having itspolarization direction selectively rotated in the correspondingliquid-crystal cell. After passing through the liquid-crystal cell, thespecified light passes through the substrate and impinges on a suitablylocated polarization analyzer. Because the polarization direction of theselected light is selectively rotated in the liquid-crystal cell, theintensity of the specified light is selectively altered as it passesthrough the polarization anaylzer so as to present part of an image.

[0024] More particularly, the liquid crystal used to form theliquid-crystal cells of the present light modulator normally consists ofrod-like molecules oriented such that linearly polarized light istransmitted through the liquid crystal with a polarization direction inaccordance with the orientation of the liquid-crystal molecules. Theoptical axis of the transmitted, polarized light normally corresponds tothe long axes of the molecules. When an electric field is applied acrossa layer of the liquid-crystal material, the orientation of the moleculesis a function of the electric field. The molecules are preferablyoriented with their long axes roughly orthogonal to the direction of theelectric field under the condition of maximum electric field.

[0025] Under the influence of the electric field, the long axes of theliquid-crystal molecules rotate. The amount of molecular orientationrotation increases with the strength of the electric field. Thepolarization direction of the linearly polarized light passing throughthe liquid-crystal layer varies with the molecular orientation rotation.The rotation of the polarization direction thereby varies from zero whenthe field strength is zero to a maximum value when the field strength isat its maximum. Upon passing through a suitably located polarizationanalyzer, the intensity of the transmitted light similarly varies withthe amount of field-induced rotation.

[0026] The benefits of the present active-matrix light modulator can beseen by examining how the transistors and liquid-crystal cells areoperated in accordance with the invention to assist in presenting animage. Starting with all the transistors in their non-conductiveconditions, selected ones of the transistors are sequentially bombardedwith electrons according to an image pattern at a dosage and averageenergy that cause each selected transistor to enter its conductivecondition. During the sequential electron bombardment of the selectedtransistors, all of the transistors are disabled. Accordingly, theliquid-crystal cells do not yet start to assist in presenting an imagecorresponding to the image pattern. The sequential electron bombardmentis preferably done with a scanning electron beam of the electron-beamsystem.

[0027] Each selected transistor is subsequently enabled in a writingmanner that results in the polarization direction of the specified lightbeing selectively rotated in the corresponding liquid-crystal cell. Whenthere are multiple selected transistors, all of the selected transistorsare enabled substantially simultaneously in the writing manner. Thisresults in the polarization directions of the specified light beingselectively rotated substantially simultaneously in all of theliquid-crystal cells corresponding to the selected transistors. Using asuitably located polarization analyzer, the combination of theliquid-crystal cells, substrate, and polarization analyzer therebypresent the entire image at substantially the same instant. Operating inthis manner enables the active-matrix light modulator of the inventionto avoid undesirable time-varying image artifacts.

[0028] The current image pattern is preferably erased in preparation forthe next image in a sequence of images. At the end of the image-patternerasure, all of the transistors are again in their non-conductiveconditions. The image-pattern erasure normally involves an operation inwhich all of the transistors are bombarded substantially simultaneouslywith electrons at a suitable average energy. The simultaneous electronbombardment of all the transistors is preferably done with an additionalelectron beam of the electron-beam system.

[0029] The transistors are normally field-effect devices of thethin-film type. Each such field-effect transistor contains first andsecond laterally separated source/drain regions, a semiconductor layer,and a gate element. Semiconductor material of the semiconductor layerextends between the source/drain regions. The gate element, whichcontrols the transistor's conductive and non-conductive conditions, issituated at least above the semiconductor material between thesource/drain regions. The first source/drain region of each transistoris in electrical communication with the corresponding liquid-crystalcell.

[0030] Each field-effect transistor is preferably a virtual-gatetransistor in that its gate element consists substantially fully ofdielectric material. In particular, the gate element of each transistoris preferably formed with a first gate dielectric layer and an overlyingsecond gate dielectric layer which receives electrons during theelectron-bombardment operations. The second gate dielectric layer iscapable of storing electrical charge and, upon being bombarded withelectrons, of having the amount of stored electrical charged change soas to selectively induce the channel-region electric field for thetransistor's conductive or non-conductive condition. This is typicallyachieved by implementing the second gate dielectric layer withdielectric material having a secondary electron emission coefficient (i)less than 1 when the primary electron energy is below a crossover valueand (ii) greater than 1 when the primary electron energy is above thecrossover value in a range up to some higher energy value.

[0031] Spacer elements are preferably situated between theliquid-crystal cells. The spacer elements provide substantially uniformliquid-crystal cell thickness. This avoids image gray-scalenon-uniformities due to changes in optical path length of the modulatedlight.

[0032] A flexible membrane preferably lies between the transistors, onone hand, and the liquid-crystal cells, on the other hand. The membraneimproves the hermetic sealing between, and acts as a contaminationbarrier between, the liquid-crystal cell environment and the vacuum towhich the transistors are subjected.

[0033] The present active-matrix light modulator operates in a highlyefficient manner. In addition to avoiding undesirable image artifacts,the modulator's spatial resolution is largely not limited by parasiticimpedances of addressing electrodes. The image is highly uniform. Theoperating life is long due to the elimination of liquid-crystaldegradation caused by residual DC voltage across image-carrying cells ofprior electron-beam-addressed light modulators.

[0034] Two factors enable the AMLCD spatial resolution to be very highin the light modulator of the invention. Firstly, bus electrodes and theassociated bus-electrode area are not needed in the present lightmodulator. Secondly, the interval time for transferring (writing) eachimage pattern can be comparatively long, thereby allowing the capacitorsthat incorporate the liquid-crystal cells sufficient time to fullycharge to the desired values. The transistors can be made quite small.Aliasing artifacts due to active-matrix array spatial resolution beingless than addressing resolution are reduced in the present lightmodulator. The present invention thus provides a large advance over theprior art.

BRIEF DESCRIPTION OF THE DRAWINGS

[0035]FIG. 1a is a cross-sectional side view of anelectron-beam-addressed active-matrix spatial light modulator, includingelectron-beam system, in accordance with the invention.

[0036]FIG. 1b is a circuit diagram of the light modulator, includingcontrol component, of FIG. 1a.

[0037]FIG. 2 is a plan view of sixteen subpixels, where four subpixelsin a square form a pixel in the light modulator of FIGS. 1a and 1 b.

[0038]FIG. 3 is a graph of source-drain current as a function of gatevoltage for a field-effect transistor in the active matrix of the lightmodulator of FIGS. 1a and 1 b.

[0039]FIG. 4 is a graph of secondary electron emission coefficient as afunction of primary electron energy for the dielectric material of thedelta coatings of the gate elements of the active-matrix transistors inthe light modulator of FIGS. 1a and 1 b.

[0040]FIG. 5 is a timing diagram for typical operation of the lightmodulator of FIGS. 1a and 1 b.

[0041]FIGS. 6a-6 c and 6 e are cross-sectional side views representingsteps in fabricating a mandrel substrate for use in manufacturing thelight modulator of FIG. 1a. FIG. 6d is a plan view of the intermediatestructure of FIG. 6c.

[0042]FIGS. 7a, 7 b, 7 d, and 7 f-7 j are cross-sectional side viewsrepresenting initial steps in a process for manufacturing the lightmodulator of FIG. 1a in accordance with the invention utilizing themandrel substrate fabricated according to the process of FIGS. 6a-6 e.FIGS. 7c and 7 e are plan views of the respective intermediatestructures of FIGS. 7b and 7 d. FIGS. 7a-7 k specifically illustrateformation of the display electrodes and thin flexible membrane.

[0043]FIGS. 8a-8 m are cross-sectional side views representing furthersteps, starting from the stage of FIG. 7j, in the process formanufacturing the light modulator of FIG. 1a according to the invention.FIGS. 8a-8 m specifically illustrate formation of the active-matrixthin-film transistors.

[0044]FIGS. 9a, 9 c, and 9 d are cross-sectional side views representingyet further steps, starting from the stage of FIG. 8m, in the processfor manufacturing the light modulator of FIG. 1a according to theinvention. FIG. 9b is a side, partial cross-sectional view that showshow a roller is utilized at the stage of FIG. 9a. FIGS. 9a-9 dspecifically illustrate release of the mandrel substrate.

[0045]FIGS. 10-13 are views representing later steps, starting from thestage of FIG. 9d, in the process for manufacturing the light modulatorof FIG. 1a according to the invention. FIGS. 10 and 12 are plan views.FIGS. 11 and 13 are cross-sectional side views. FIGS. 10-13 illustrateformation of the liquid-crystal cells and installment of the modulatorsubstrate.

[0046]FIGS. 14 and 15 are schematic views of projection systems thatemploy the light modulator of FIGS. 1a and 1 b.

[0047] Like reference symbols are used in the drawings and in thedescription of the preferred embodiments to represent the same, or verysimilar, item or items.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0048] The present invention furnishes a reflective liquid-crystal lightmodulator addressed by an array of thin-film transistors, wherein eachdisplay element has electrical and mechanical isolation from adjacentand proximate display elements. Image information is provided to theactive array by means of a scanning electron beam.

[0049] Referring to the drawings, FIGS. 1a and 1 b (collectively “FIG.1”) together illustrate a reflective liquid-crystal light modulator inaccordance with the invention. The light modulator of FIG. 1 includes athin flexible membrane 200, an active matrix 201 disposed along one side(the upper side in FIG. 1a) of membrane 200, a two-dimensional array ofdisplay electrodes 31 disposed along the other side (the lower side inFIG. 1a) of membrane 200, electrically conductive means 49 forelectrical communication between active matrix 201 and displayelectrodes 31, a layer 70 of liquid crystal divided into atwo-dimensional array of liquid-crystal cells 202 respectivelycorresponding to display electrodes 31, an electrically insulatingtransparent modulator substrate 90, a common transparent electrode 91situated on substrate 90, a control component 203, and an electron-beamsystem formed with a writing electron gun 400 and an erasing gun 500.Writing electron gun 400 generates a scanning electron beam 401 foraddressing active matrix 201. Erase electron gun 500 generates anelectron beam 501 for use in flood erasing matrix 201.

[0050] Components 90, 91, 200, 201, and 202 form a light-modulatorstructure. A hermetically sealed vacuum envelope (not shown), includinga transparent faceplate (also not shown), encloses the modulatorstructure and electron guns 400 and 500. Means for providing appropriateelectrical signals to the components inside the vacuum envelope aresituated outside the vacuum envelope. A pressure typically in thevicinity of 10⁻⁶ torr is present inside the vacuum envelope. Flexiblemembrane 200 provides a seal barrier between active matrix 201 andliquid-crystal cells 202.

[0051] Liquid-crystal layer 70 lies between display electrodes 31, onone hand, and common electrode 91, on the other hand. Electricallyinsulating spacers 43 laterally separate liquid-crystal cells 202 fromone another in layer 70. Spacers 43 also provide a uniform spacingbetween common electrode 91 and display electrodes 31. This enables thethickness of liquid-crystal layer 70 to be highly uniform, therebysubstantially avoiding gray-scale non-uniformities that could otherwisearise from changes in the optical path length of the modulated light.

[0052] Active matrix 201 contains a two-dimensional array oftwo-terminal thin-film field-effect transistors 204 respectivelycorresponding to liquid-crystal cells 202. Each thin-film transistor(“TFT”) 204 is a virtual-gate device consisting of a pair of laterallyseparated source/drain regions (or pads) 51 and 52, a pair ofsource/drain electrodes 53 and 54 respectively contacting source/drainregions 51 and 52, a semiconductor layer 57 extending between andpartially over source/drain regions 51 and 52, and a virtual gateelement formed with a first gate dielectric layer 58 and a second gatedielectric layer 59 referred to here as a delta coating. First gatedielectric layer 58 lies on semiconductor layer 57, including thesemiconductor material extending between source/drain regions 51 and 52.Delta coating 59 is situated on gate dielectric layer 58.

[0053] Source/drain regions 51 and 52 variously function as source anddrain during light-modulator operation. For convenience, source/drainregion 51 is sometimes referred to below as “source region” (or simply“source”) 51, and source/drain region 52 is sometimes referred to belowas “drain region” (or simply “drain”) 51. Similarly, source/drainelectrodes 53 and 54 are sometimes referred to below respectively assource electrode 53 and drain electrode 54.

[0054] The combination of each TFT 204, corresponding underlying displayelectrode 31, corresponding underlying liquid-crystal cell 202, and theunderlying parts of common electrode 91 and substrate 90 constitute asubpixel. Each pixel of the light modulator of FIG. 1 is formed withfour subpixels arranged laterally in a square as shown in FIG. 2. Asaddressing electron beam 401 sequentially scans the light-modulatorarray, four TFTs 204 thus receive the image information conveyed byelectron beam 401 in modulating one pixel. This characteristic of thelight modulator of FIG. 1 improves image quality by minimizingstair-stepping and blocky appearances of images containing diagonallines and features.

[0055] More particularly, the light-modulator structure of FIG. 1 isallocated into an array or rows and columns of pixels as indicated inFIG. 2. The subpixels are similarly arranged in rows and columns. Thesubpixels have an average subpixel width in a first lateral direction,e.g., the vertical direction in FIG. 2. The average subpixel width inthe first lateral direction is typically the average width of TFTs 204,specifically their gate elements (described further below), in the firstlateral direction.

[0056] As described below, electron beam 401 of writing electron gun 401scans TFTs 204 during transistor writing operations. In scanning TFTs204 in a second lateral direction, e.g., the horizontal direction inFIG. 2, generally perpendicular to the first lateral direction, beam 401has a beam width in the first lateral direction. As indicated below inconnection with FIG. 4, beam 401 provides electrons having a generallyGaussian spatial distribution perpendicular to the direction of beamtravel. Based on this Gaussian electron distribution, the beam width isthe Gaussian distribution width at which the electron current density inbeam 401 is one half (50%) of the maximum electron current density inbeam 401.

[0057] The beam width is normally approximately, at least, the averagepixel width in the first lateral direction and, in the case of FIG. 2where each pixel has two subpixels in line with each other in the firstlateral direction, twice the average subpixel width in the first lateraldirection. Twice the subpixel width is defined as the lateral dimensionbetween centers of the two transistor gate elements (pitch) plus thelateral width dimension of the transistor gate element in the samelateral dimension. When the transistor gate-element dimension is not thesame for the first and second lateral directions, the average pixelwidth is the greater of the two dimensions. For the more general case inwhich a pixel contains two or more subpixels in line with one another inthe first lateral direction, the beam width is at least twice the pixelwidth. Where a pixel contains three or more subpixels in line with oneanother in the first lateral direction, the beam width is not less thanthree times the average subpixel width. Hence beam 401 scans along aline whose width is at least twice the average subpixel width and thusat least twice the average transistor width.

[0058] Source/drain regions 51 and 52 of each TFT 204 consist of heavilydoped n-type amorphous semiconductor material, preferably silicon.Semiconductor layer 57 consists of substantially intrinsic (undoped)semiconductor material, likewise preferably silicon. Source/drainelectrodes 53 and 54 are formed with metal, typically chromium. Gatedielectric layer 58 of each TFT 58 is typically silicon nitride (Si₃N₄)but can be formed with other electrical insulators such as silicon oxide(SiO₂). Delta coating 59 of each TFT 204 consists, as discussed furtherbelow, of dielectric material which emits low-energy secondary electronsat a relatively high areal emission rate when impacted by primaryelectrons of sufficient kinetic energy. For example, delta coatings 59are typically formed with magnesium oxide (MgO).

[0059] The light modulator of FIG. 1 modulates visible light, typicallycolor light. For operation in a light-reflective mode with color light,the modulator can be typically provided with an appropriate colorfilter. The modulated visible light can be white light.

[0060] Data information is applied to the gate element of each TFT 204in order to vary the source-drain current I_(SD) through that TFT 204 asshown in FIG. 2. Source-drain current I_(SD) is a function of gatevoltage V_(D). For typical TFT geometry, there is a region in whichsource current I_(SD) varies fairly linearly (on a logarithmic scale)with gate voltage V_(G). The operating TFT range is the gate-voltagerange between the threshold voltage V_(th) at which TFTs 204 turn on(start to conduct current) and the voltage V_(sat) at which TFTs 204saturate.

[0061] The number of secondary electrons emitted from each delta coating59 as a ratio of secondary electrons to incident primary electronsincreases with increasing energy (electron volts) of the primaryelectrons. Since the kinetic energy of secondary electrons is very low,many secondary electrons return to a delta coating 59 unless there is astrong electric field adjacent the emitting surface to accelerateemitted electrons away from the emitting surface. If the averageprimary-electron energy is sufficiently high that the number ofsecondary electrons emitted by a delta coating 59 exceeds the totalnumber of primary and secondary electrons collected by that coating 59,a positive charge is produced on that coating 59. Conversely, a negativecharge is produced on a delta coating 59 if the average primary-electronenergy is sufficiently low that the total number of primary andsecondary electrons collected by that coating 59 exceeds the number ofsecondary electrons emitted by that coating 59. The polarity of chargeon each delta coating 59 is thus controlled by controlling the averageenergy of the primary electrons.

[0062] When a subpixel is being addressed for a writing operation, apositive charge is induced on that subpixel's delta coating 59 bysupplying primary electrons at a relatively high average energy fromelectron beam 401 of writing electron gun 400. In simultaneously erasingall of the subpixels, negative charges are induced on all of deltacoatings 59 by furnishing primary electrons at a relatively low averageenergy from electron beam 501 of erasing electron gun 500. The energy ofelectron beam 401 or 501 can be approximated by the difference betweenthe potential of the primary electrons emitted from the electron guncathode and the potential of a delta-coating surface at which theelectrons impact.

[0063]FIG. 4 illustrates how the secondary electron emission coefficientδ, i.e., the ratio of emitted secondary electrons to collected primaryand secondary electrons, varies with the average energy V_(PE) ofprimary electrons that impact a surface formed with the dielectricmaterial of delta coatings 59. As shown in FIG. 4, there are twopotentials at which a delta-coating surface stabilizes. When the averageprimary-electron energy V_(PE) is low, i.e., less than a crossover valueV_(CR1) below which coefficient δ is less than 1, the surface collectsprimary and secondary electrons until the surface potential isapproximately the same as the electron-gun cathode potential. When theaverage primary-electron energy V_(PE) is sufficiently high, i.e.,greater than V_(CR1) at a value in the range (extending to some highervalue) where coefficient δ is greater than 1, and the collection fieldadjacent the surface is sufficient to collect most of the emittedsecondary electrons, the surface charges to the potential of theadjacent collector. If the dosage (number) of electrons furnished by theelectron beam is insufficient, either because the electron beam currentis low or/and the time during which the electron beam dwells on deltacoating 59 is short, coating 59 charges toward one of the two stablepotentials. The time that a scanning electron beam dwells on anylocation is typically determined by the preferred video rate and numberof pixels in the display. The variable current in the electron beamtherefore determines the variable charge on delta coating 59.

[0064] Each TFT 204 has a channel region consisting of the semiconductormaterial situated between source/drain regions 51 and 52. The electricfield in the channel region of each TFT 204 varies with the amount ofelectrical charge on that TFT's delta layer 59. Each TFT 204 is in anon-conductive condition when its channel-region electric field issubstantially insufficient for (current) conduction. This arises whendelta coating 59 of that TFT 204 is negatively charged or is positivelycharged below a threshold level necessary for current to flow throughthat TFT's channel region.

[0065] When delta coating 59 of a TFT 204 is positively charged to atleast the threshold level, the channel-region electric field for thatTFT 204 becomes sufficiently high for it to conduct current via acarrier channel extending along the top of the semiconductor materialbetween source/drain regions 51 and 52. The amount of current which canflow through the channel increases with increasing positive charge ondelta coating 59 up to a saturation level as indicated in FIG. 3. EachTFT 204 is thus in a conductive condition when its channel-regionelectric field is sufficient for at least partial (current) conduction.The conductive conduction for each TFT 204 varies between (a) alow-field condition in which its channel-region electric field is justsufficient for conduction to occur and (b) a high-field condition atwhich its channel-region electric field is highest depending on variousphysical and operational parameters so that a maximum amount of currentcan flow through that TFT 204.

[0066] Delta coatings 59 of selected ones of TFTs 204 are provided withselected amounts of positive charge in accordance with an image patternduring a transistor writing operation by sequentially bombardingcoatings 59 of those selected TFTs 204 with electrons from scanningelectron beam 401 of writing electron gun 400 at an electron dosage andaverage electron energy V_(PE) suitable for placing each selected TFT204 in its conductive condition at a selected level ranging from itslow-field condition to its high-field condition. Average electron energyV_(PE) during the transistor writing operation is greater than crossovervalue V_(CR1) and at a suitable point in the range where secondaryelectron emission coefficient δ exceeds 1. The electron dosage providedto delta coating 59 of each selected TFT 204 depends on theelectron-beam current and dwell time during which electrons fromelectron beam 401 bombard that coating 59. The dwell time is typicallythe same for coatings 59 of all selected TFTs 204. Accordingly, theelectron dosage is controlled from selected TFT 204 to selected TFT 204by appropriately controlling the electron-beam current for each selectedTFT 204. Subsequent to the transistor writing operation, a writingoperation (described further below) is performed on liquid-crystal cells202 corresponding to selected TFTs 204 for charging the capacitors thatincorporate those cells 202 in accordance with the image pattern ofselected TFTs 204.

[0067] As described further below, a transistor erase operationpreferably consists of (a) an initial part in which each selected TFT204 is returned to its non-conductive condition, (b) an intermediatepart in which all of TFTs 204 are simultaneously placed in theirconductive conditions, normally at their high-field conditions, forsimultaneously discharging all of liquid-crystal cells 202, and (c) afinal part in which all of TFTs 204 are simultaneously returned to theirnon-conductive conditions. The three parts of the transistor eraseoperation are performed with erase electron gun 500.

[0068] During the initial part of the transistor erase operation,electron beam 501 is directed substantially simultaneously toward deltacoatings 59 of all TFTs 204 in a flood manner. Because delta coatings 59of selected TFTs 204 were charged positively during a transistor writingoperation to a level at or in excess of the threshold level whilecoatings 59 of the remaining (unselected) TFTs 204 are normally chargedto a common-plane reference potential V_(ref) typically at 0 V and, inany case, are not charged to at least the threshold level, electronsfrom electron beam 501 largely only strike coatings 59 of selected TFTs204 during the initial part of the transistor erase. In particular,delta coatings 59 of selected TFTs 204 are simultaneously bombarded withelectrons from beam 501 at an electron dosage and average electronenergy suitable for returning all of selected TFTs to theirnon-conductive conditions. Average electron energy V_(PE) is less thancrossover value V_(CR1) and at a value in the range where secondaryelectron emission coefficient δ is below 1. The dosage during theinitial part of the transistor erase depends on the electron-beamcurrent and dwell time during which electrons from beam 501simultaneously bombard coatings 59 of selected TFTs 204. Theelectron-beam current is set at a value sufficiently high to ensure thatany selected TFT 204 in its high-field condition returns to itsnon-conductive condition. All of TFTs 204 are in their non-conductiveconditions at the end of the initial part of the transistor erase.

[0069] The intermediate part of the transistor erase operation consistsof simultaneously bombarding delta coatings 59 of all TFTs 204 withelectrons from electron beam 501 at an electron dosage and averageelectron energy suitable for placing all of TFTs 204 in their conductiveconditions, again normally their high-field conditions. Average electronenergy V_(PE) for the intermediate part of the transistor erase isgreater than crossover value V_(CE1) and at a suitable location in therange where secondary electron emission coefficient δ exceeds 1. Thedosage is controlled by appropriately choosing the electron-beamcurrent. Subsequent to the transistor erase operation, an eraseoperation (described further below) is performed to simultaneouslydischarge the capacitors that incorporate all of liquid-crystal cells202.

[0070] The final part of the transistor erase operation consists ofsimultaneously bombarding delta coatings 59 of all TFTs 204 withelectrons from electron beam 501 at an electron dosage and averageelectron energy suitable for placing all of TFTs 204 in theirnon-conductive conditions. Average electron energy V_(PE) for the finalpart of the transistor erase is less than crossover value V_(CE1) and ata suitable value where secondary electron emission coefficient δ isbelow 1. The dosage is controlled by appropriately choosing theelectron-beam current. TFTs 204 are now ready for another transistorwriting operation.

[0071] Conductive means 49 which provides electrical communicationbetween active matrix 201 and display electrodes 31 consists of TFTsource electrodes 53. In particular, each display electrode 31 iselectrically connected to corresponding TFT 204 via its source electrode53 that carries source/drain current I_(SD) at a source voltage V_(S).Each display electrode 31 is situated on corresponding liquid-crystalcell 202. Consequently, each TFT 204 electrically communicates withcorresponding liquid-crystal cell 202 by way of the combination ofcorresponding display electrode 31 and that TFT's source electrode 53.

[0072] Drain electrodes 54 of all TFTs 204 are electrically connectedtogether to receive a common drain voltage V_(D) from control component203 on a line 209 as shown in FIG. 1b. Control component 203 consists ofa switch 210 and a composite reference-voltage/high-impedance source 220formed with a high-impedance section 221 and three reference-voltagesections 222, 223, and 224. High-impedance section 221 provides ahigh-impedance signal V_(HZ) at a voltage typically equal to 0 V (groundreference). Reference-voltage section 222 supplies a low-impedancehigh-positive cell-writing voltage V_(CW+). Reference-voltage section223 supplies a low-impedance high-negative cell-writing voltage V_(CW−).Reference-voltage section 224 supplies a low-impedance low cell-erasevoltage V_(CE) at a value normally approximately midway between theV_(CW+) and V_(CW−) values. In a typical embodiment of the lightmodulator of FIG. 1, writing voltage V_(CW+) is +5 V, erase voltageV_(CE) is 0 V, and writing voltage V_(CW−) is −5 V.

[0073] Responsive to control signals CTL, switch 210 electricallyconnects line 209 to one of reference-voltage/high-impedance sections221-224. Drain electrodes 54 of TFTs 204 therefore all simultaneouslyreceive drain voltage V_(D) at (a) high-positive writing value V_(CW+)during certain time periods, (b) erase value V_(CE) during other timeperiods, and (c) high-negative writing value V_(CW−) during yet othertime periods. As discussed further below, drain voltage V_(D) issupplied at erase value V_(CE) for simultaneously erasing all ofliquid-crystal cells 202 during the erase portion of every image datafield. Drain voltage V_(D) is supplied at high-positive writing valueV_(CW+) for simultaneously writing selected ones of cells 202 duringevery other image data field, and at high-negative writing value V_(CW−)for simultaneously writing selected ones of cells 202 during eachremaining alternate image data field so that the average DC voltageacross cell 202 is approximately zero. This prevents liquid-crystalcells 202 from incurring undesirable DC offset.

[0074] Drain electrodes 54 of TFTs 204 also simultaneously receive drainvoltage V_(D) at high-impedance value V_(HZ) during further time periodsreferred to here as disablement time periods or intervals. The impedancethat characterizes high-impedance voltage V_(HZ) is very high,effectively infinite. Connecting drain electrodes 54 through line 209and switch 210 to receive high-impedance signal V_(HZ) thereforeeffectively open circuits all of TFTs 204 regardless of whether each TFT204 is in its conductive or non-conductive condition. As a result, allof TFTs 204 are disabled, i.e., do not significantly conduct current,when switch 210 connects line 209 to the V_(HZ) position.

[0075] Each liquid-crystal cell 202 extends between correspondingdisplay electrode 31 and common electrode 91 situated on substrate 90.Common electrode 91 is connected to an electrical line 441 that receivescommon-plane reference voltage V_(ref), again typically 0 V.Liquid-crystal cells 202 preferably consist of nematic liquid crystalwith negative dielectric anisotropicity. Common electrode 91 consists ofindium tin oxide (“ITO”). Substrate 90, which forms the faceplate forthe light modulator of FIG. 1, consists of glass.

[0076] The light modulator of FIG. 1 operates in a reflective mode withdisplay electrodes 31 being light reflective at least along their flatliquid-crystal-contacting surfaces (lower surfaces in FIG. 1a).Double-headed arrow 912 in FIG. 1a indicates linearly polarized visiblelight that impinges on the front surface (lower surface in FIG. 1a) ofsubstrate 90 at the front of the light modulator, passes throughsubstrate 90 and common electrode 91, passes through a liquid-crystalcell 202 where the light's polarization direction may undergo rotationdepending on voltage V_(LC) (not indicated in FIG. 1a) across that cell202, is reflected off the liquid-crystal-contacting surface ofcorresponding display electrode 31, passes back through that cell 202where the light's polarization direction may undergo further rotation,and passes back through common electrode 91 and substrate 90 and out thefront of the light modulator.

[0077] Voltage V_(LC) across a liquid-crystal cell 202 is a function ofthe amount of charge provided through corresponding TFT 204 tocorresponding display electrode 31 during cell writing operations(described further below). Each liquid-crystal voltage V_(LC) variesfrom approximately 0 V to V_(CW+)-V_(CE) (or V_(CE)-V_(CW+)), typically5 V. The polarization direction of the plane polarized visible lightpassing twice through a cell 202, once on incidence and the second timeon reflection, undergoes largely no rotation when voltage V_(LC) forthat cell is zero. When voltage V_(LC) is at its maximum, thepolarization direction undergoes a maximum rotation. Each liquid-crystalcell 202 thus operates from (i) a low-rotation condition in which thepolarization direction of the light passing through that cell 202rotates a first amount as little as zero to (ii) a high-rotationcondition in which the polarization direction of the light passingthrough that cell 202 rotates a second amount greater than the firstamount. The maximum rotation of the polarization direction on eachpassage through a cell 202 is typically 45° for a total maximum rotationof 90°.

[0078] Each liquid-crystal cell 202 in combination with displayelectrode 31 and the underlying part of common electrode 91 forms aliquid-crystal capacitor C_(LC) as shown schematically in FIG. 1b. Theparticular cells 202 which correspond to selected TFTs 204 placed intheir conductive conditions in accordance with the image pattern arereferred to here as selected liquid-crystal cells 202. The combinationof a selected liquid-crystal cell 202, corresponding display electrode31, and the underlying part of common electrode 91 is then referred toas a selected liquid-crystal cell capacitor C_(LC).

[0079] A storage capacitor C_(S) is formed with each display electrode31, the overlying part of storage capacitor dielectric layer 41, and thefurther overlying part of ground plane 44 as also shown in FIG. 1a. Eachstorage capacitor C_(S) corresponds to, and is connected electrically inparallel with, one of liquid-crystal capacitors C_(LC). Storagecapacitors C_(S) provides additional storage capacity for liquid-crystalcapacitors C_(LC) so that minor charge leakage from cell capacitorsC_(LC), caused by possible fabrication defects, is compensated for byreserve charge in storage capacitors C_(S). This ensures that desiredimage gray level is maintained.

[0080] During a cell writing operation (performed after a transistorwriting operation), all of selected liquid-crystal capacitors C_(LC) andcorresponding storage capacitors C_(S) are charged by respectivelyproviding currents I_(SD) through source electrodes 53 of selected TFTs204 to selected cell capacitors C_(LC) and corresponding storagecapacitors C_(S) for a specified time period. The charge provided toeach selected liquid-crystal capacitor C_(LC) and corresponding storagecapacitor C_(S) depends on the magnitude and time duration of currentI_(SD) flowing through corresponding selected TFT 204.

[0081] Selected TFTs 204 are, during the cell writing operation, intheir conductive conditions at selected points varying from thelow-field condition to the high-field condition in accordance with theimage pattern. Drain voltage V_(D) is provided to drain electrodes 54 ofall TFTs 204, including selected TFTs 204, at the same value V_(CW+) orV_(CW−) during the cell writing operation. Consequently, the magnitudesof currents I_(SD) flowing through selected TFTs 204 vary according towhere the conductive condition of each selected TFT 204 is in theelectric-field range extending from the low-field condition to thehigh-field condition. Since the capacitor charging time is the same forall of selected liquid-crystal capacitors C_(LC) and correspondingstorage capacitors C_(S), the charge provided to each selected cellcapacitor C_(LC) and corresponding storage capacitor C_(S) during thecell writing period varies in accordance with the image patternaccording to where the conductive condition of corresponding selectedTFT 204 is in the electric-field range extending from the low-fieldcondition to the high-field condition.

[0082] Membrane 200, which isolates liquid-crystal cells 202 from thehigh-vacuum electron beam environment, consists of a lower layer 41 ofinsulating polymer disposed over display electrodes 31, a conductiveground plane 44 overlying lower insulating polymer layer 41, and anupper layer of insulating polymer 45 overlying ground plane 44. Groundplane 44 is connected in common with common electrode 91 to line 441 forreceiving common-plane reference voltage V_(ref). The thickness ofmembrane 200 is typically less than 3 μm to provide sufficientflexibility to conform to deviations in surface flatness of transparentsubstrate 90, with sufficient strength and durability due to multilayerconstruction to withstand cell processing and handling without loss ofmechanical integrity. Molded spacers 43 formed in lower insulatingpolymer 41 precisely control the thickness of liquid-crystal layer 70disposed between light-reflective display electrodes 31 and ITO-coatedglass faceplate 90.

[0083] A passivation dielectric layer 46 is situated on upper insulatingpolymer layer 45. Source electrodes 53 connect display electrodes 31 toTFTs 204 via openings through multilayer membrane 200 and passivationlayer 46. The laminated light-modulation structure of FIG. 1a furtherincludes a collector grid structure formed with a collector grid 62 andan underlying grid dielectric 63. Although not shown in FIG. 1a, deltacoatings 59 preferably form a continuous layer that extends under griddielectric 63. Subject to the presence of the continuous delta layer,grid dielectric 63 extends over passivation layer 46. TFTs 204 are alsosituated over passivation layer 46 and are exposed through openings inthe collector grid structure. A collector potential V_(coll) is suppliedon an electrical line 600 connected to collector grid 62.

[0084] Referring to FIG. 5, it illustrates a timing diagram thatfacilitates understanding typical operation of the light modulator ofFIG. 1. FIG. 5 presents timing curves for:

[0085] a. Reference potential V_(ref) on line 441 connected to commonelectrode 91 and ground plane 44,

[0086] b. Collector voltage V_(coll) on line 600 connected to collectorgrid 62,

[0087] c. Cathode voltage V_(wgk) on writing gun cathode 402 of writingelectron gun 400,

[0088] d. Beam current I_(wb) of scanning electron beam 401 of writingelectron gun 400,

[0089] e. Cathode voltage V_(egk) on erase gun cathode 502 of eraseelectron gun 500,

[0090] f. Beam current I_(eb) of flood electron beam 501 of eraseelectron gun 500,

[0091] g. Charge δ on a delta coating 59,

[0092] h. Drain voltage V_(D),

[0093] i. Liquid-crystal cell voltage V_(LC), and

[0094] j. Display brightness.

[0095] During a first time interval constituting a subset of the timerequired for a video field, reference potential V_(ref) is set to 0 V.Collector potential V_(coll) is set to 10 V relative to referencepotential V_(ref) to provide a high collection field at 10 V/μm. Erasegun electron beam 501 is off. Writing gun cathode potential V_(wgk) isset at −200 V with respect to reference voltage V_(ref). Averageelectron energy V_(PE) of writing beam 401 is greater than firstelectron crossover potential V_(CR1), and delta layer 59 of eachselected TFT 204 charges in the positive direction toward collectorpotential V_(coll). With the distribution of electron current I_(wb) inscanning electron beam of writing electron gun 400 being substantiallyGaussian as shown in FIG. 4, beam 401 sequentially scans each horizontalline in the TFT array and induces positive charge on delta coating 59 ofeach selected TFT 204 by means of secondary electron emission as shownin FIG. 3. Delta coating 59 of each selected TFT 204 charges (+) towardadjacently located collector potential V_(coll). The magnitude of theinduced positive charge (δ-charge) is proportional to electron currentI_(wb) in writing electron beam 401 and the dwell time of beam 401. Themagnitude of electron-beam current I_(wb) is determined by the inputpicture information. The electron-beam dwell time on any TFT 204 isinversely proportional to the number of pixels in the display, but isconstant for any specific resolution, e.g., less than 1.5 nsec for a2500-line display.

[0096] Each delta coating 59 remains charged to the written potentialuntil the deposited charge is erased by aerial electrons since there isno conducting discharge path. During this first time interval, voltageV_(D) on drain electrodes 54 is set to high-impedance off potentialV_(HZ). Although there is charge-induced electric field on the TFTchannel regions, there is no source current to charge liquid-crystalcell capacitors C_(LC) and storage capacitors C_(S). Consequently, noimage is displayed as the entire video field is written into TFTs 204.

[0097] During a second time interval constituting a subset of the timerequired for the video field, after the entire TFT array is written,with the charge pattern representing a field of video information storedon delta coatings 59 in the TFT array, a short positive voltage pulse isapplied to drain electrodes 54 of all TFTs 204 in the array. That is,drain voltage V_(D) is switched to value V_(CW+), typically 5 V, toprovide voltage V_(CW+) to all of the electrodes 54. Source-draincurrent I_(SD) charges each selected liquid-crystal capacitor C_(LC)formed with a selected liquid-crystal cell 202, corresponding displayelectrode 31, and the underlying part of cell common electrode 91.Source current I_(SD) also charges storage capacitor C_(S) formed inparallel to cell capacitor C_(LC) by that display electrode 31, theoverlying part of dielectric 41, and the further overlying part ofground plane 44. The duration of the V_(D) pulse is determined by thetime required to charge capacitors C_(LC) and C_(S) to maximum withmaximum gate voltage V_(G). A typical V_(D) pulse width is 1 msec.

[0098] During a third time interval, immediately following applicationof the V_(D) voltage pulse to drain electrodes 54, writing beam 401 isoff. Reference voltage V_(ref) is set to 0 V. Collector voltage V_(coll)is 10 V. Voltage V_(S) on each source electrode 53 is determined bycorresponding liquid-crystal voltage V_(LC). The typical maximum V_(LC)voltage is 5 V. Erase gun cathode voltage V_(egk) is set to 0 V relativeto reference voltage V_(ref). Erase gun electron beam 501 is gated on toproduce erase beam current I_(eb). The difference between voltageV_(egk) of erase gun cathode 502 and the potential of delta layer 59 ofeach selected TFT 204 produces a value of average electron energy V_(PE)less than first crossover potential V_(CR1). Therefore, delta layer 59of each selected TFT 204 collects electrons and charges to erase-guncathode V_(egk), now 0 V. The previously written TFT image pattern isthereby erased. Drain voltage V_(D) is set to the high-impedance offvalue V_(HZ), and no change in liquid-crystal voltages V_(LC) or imagequality occurs.

[0099] Maximum gate voltage V_(G) for a selected TFT 204 is obtainedwith maximum electron-beam current I_(wb) during the first of the threeintervals. Intermediate levels of charge on a selected liquid-crystalcapacitor C_(LC) are obtained with intermediate levels of beam currentI_(wb) to provide a gray scale.

[0100] Each liquid-crystal capacitor C_(LC), electrically connected tosource electrode 53 of corresponding TFT 204, is charged to a voltageproportional to the voltage induced by electron beam 401 on deltacoating 59 of corresponding TFT 204. This voltage is maintained due tothe high impedance of the drain driver in the off state. During thisthird display interval, polarized light 912 reflected fromliquid-crystal display electrodes 31 is intensity-modulated (displaybrightness) in accordance with the voltage charge pattern and displayedon a viewing screen.

[0101] The present invention also solves a major defect in conventionalactive matrix liquid-crystal display devices. Conventional TFT designscreate parasitic capacitance, caused by source/gate overlap, in serieswith the liquid-crystal capacitors. This parasitic capacitancedischarges the liquid-crystal capacitors and causes image degradation.Each TFT 204 in the present light modulator incorporates a virtual gatein which there is no conductive path to discharge the gate capacitor,other than by charge neutralization by aerial electrons.

[0102] Voltages V_(LC) across liquid-crystal cells 202 must bedischarged to reference potential V_(ref) following the third displayinterval, and prior to writing a subsequent field of image data. Duringa fourth time interval immediately prior to writing a new video field,writing electron beam 401 is off. Reference voltage V_(ref) is set to 0V. Collector voltage V_(coll) is 10 V. Erase gun cathode voltage V_(egk)is set to −200 V relative to reference voltage V_(ref). Voltage V_(S) oneach source electrode 53 is determined by corresponding liquid-crystalvoltage V_(LC). The typical maximum V_(LC) voltage is 5 V. Erase-gunelectron beam 501 is gated on. The difference between the potentialV_(egk) of erase gun cathode 502 and the potential of each delta layer59 produces average electron energy V_(PE) greater than crossoverpotential V_(CR1). Therefore, delta layers 59 emit secondary electronsand charge to collector potential V_(coll). A short-duration, 0-V,low-impedance voltage pulse is applied to drain electrodes 54 of allTFTs 204. That is, drain voltage V_(D) is switched to erase valueV_(CE), 0 V, to provide voltage V_(D) to all of electrodes 54. The V_(D)pulse width is of sufficient duration to discharge voltages V_(LC) onall liquid-crystal cell capacitors V_(LC). A typical discharge time is0.5 msec. The drain voltage driver is set to high-impedance off-statevalue V_(HZ). Erase gun cathode voltage V_(egk) is set to 0 V, and erasegun electron beam 501 is gated on to reset delta layers 59 to referencepotential V_(ref). The light modulator is now set to receive a new videofield.

[0103] The polarity of drain voltage V_(D) during TFT writing operations(first interval) is inverted (switched between V_(CW+) and V_(CW−))onalternate video fields. This prevents DC offset at liquid-crystal cells202.

[0104] The TFT array, isolated from liquid-crystal cells 202 by means ofdisplay electrodes 31 and isolating polymer layers 41 and 45 includingground plane 44, is a superior replacement for prior art anisotropicallyconducting substrates, conductive pin arrays, and thin (largely)dielectric membranes.

[0105] The present spatial light modulator, with the unique capabilityto separate the functions of image “write” and image “display” togetherwith fast-response liquid-crystal operating modes, offers thepossibility of ultra-high resolution displays with temporal responsecharacteristics of film-gate motion pictures.

[0106]FIGS. 6a-6 e (collectively “FIG. 6”) illustrate steps inaccordance with the invention for manufacturing a mandrel substrate onwhich the light modulator of FIG. 6 is fabricated. Referring to FIG. 6a,the starting is substrate material 10 preferably consisting of glasssuch as Corning 1737 or equivalent at a thickness of 0.7-1.1 μm. Inorder to be compatible with existing active matrix array commercialtools and processes, a blanket layer 11 of nickel is deposited bysputtering means to a thickness of 1.3 μm. The nickel-layer thickness isdefined according to calculations describing the desired opticalthickness of liquid-crystal layer 70. Nickel layer 11 is polished bychemical mechanical polishing to a high reflectivity.

[0107] Nickel layer 11 is coated with a positive tone photoresist 100typically provided by Arch Chemical Company or other commercial vendor.Photoresist 100 is exposed to actinic light through a photomask anddeveloped by conventional means to define a pattern 102 in the resistwhereby portions of nickel layer 11 are uncovered. The uncoveredportions of nickel layer 11 are chemically etched in a commerciallyavailable etchant provided by Transene Chemicals or other vendor toremove nickel metal in the regions defined by pattern 102 as shown inFIG. 6b. Glass substrate 10 is not chemically attacked by the etchingprocess. A tapering cross section of spacer mold 21 is created byaddition of 1.5 volume percent nitric acid to nickel etchant. FIG. 6c.shows mandrel 20, including spacer mold 21, after removal of photoresist100 by conventional chemical means. The diameter of spacer mold 21 istypically 1.5 μm. The depth of spacer mold 21 is controlled by thicknessof nickel layer 11 since substrate 10 is not attacked by the patternetching process. FIG. 6d shows a plan view of mandrel 20. Spacer mold 21is disposed in a regular array for which the preferred dimension betweenthe centers of mold feature 21 in the x-direction is 5 μm, and thepreferred dimension between the mold-feature centers in the y-directionis 5 μm. Mandrel 20, including spacer mold 21 and substrate 10 exposedat the bottom of spacer mold 21, is coated with a mold release 22 bysputtering means as shown in FIG. 6e. The preferred material for moldrelease 22 is a material containing amorphous carbon or boron carbide.

[0108]FIGS. 7a-7 j (collectively “FIG. 7”) illustrate initial steps inaccordance with the invention for manufacturing the light modulator ofFIG. 1a using mandrel substrate 20 fabricated according to process ofFIG. 6. FIG. 7 specifically shows a preferred process sequence forfabrication of a flexible conformal film, incorporating an array oftransistors disposed on a first side, and a corresponding array ofdisplay electrodes disposed on a second side. In FIG. 7a, a layer ofaluminum 30 is deposited over mandrel 20 to a preferred thickness of 1μm by sputtering means, and is coated with a positive tone photoresist100. Photoresist 100 is exposed to actinic light through a photomask,with alignment and optical registration to superimpose a pattern 103 topreviously defined pattern 102 as shown in FIG. 7b, and developed byconventional means to define a pattern 103 in resist 100 wherebyportions of aluminum layer 30 are uncovered. FIG. 7c is a plan view ofphotopattern 103. The uncovered portions of aluminum layer 30 arechemically etched with a commercially available etchant provided byTransene Chemicals or other vendor to remove aluminum metal in theregions defined by pattern 103 to define display electrodes 31 as shownin FIG. 7d. Mold release 22 is not chemically attacked by the aluminumetchant. Display electrodes 31 are disposed in a regular array overmandrel 20 as shown in FIG. 7e, a plan view of display electrodes 31disposed on mandrel 20, where the preferred dimension between thecenters of display electrodes 31 in the x-direction is 5 μm, and thepreferred dimension between the display-electrode centers in they-direction is 5 μm.

[0109] Mandrel 20, together with the display electrode array and spacermold 21, is coated with a liquid polymer material, such as PI 2610supplied by HD Microsystems, and cured at 350° C. to a preferred filmthickness of 0.5-1 μm to form display element storage capacitordielectric 41, and spacer elements 43 as shown in FIG. 4b. Polymer 41adheres to display electrodes 31, but does not adhere to mold release22. A layer 42 of chromium is deposited by sputter means over capacitordielectric 41 to a film thickness of 100 nm as shown in FIG. 7f.Chromium layer 42 is coated with a positive tone photoresist 100 andexposed to actinic light through a photomask, with alignment and opticalregistration to superimpose pattern 104 to previously defined pattern103 as shown in FIG. 7g, and developed by conventional means to define apattern 104 in resist 100 whereby portions of chromium layer 42 areuncovered. The uncovered chromium is chemically etched with acommercially available etchant provided by Transene Chemicals or othervendor to remove the chromium metal in the regions defined by pattern104 to define ground plane 44 as shown in FIG. 7h. A second layer ofliquid polymer material, such as PI 2610 supplied by HD Microsystems, iscoated over ground plane 44 and the exposed portions of storagecapacitor dielectric 41, and cured at 350° C. to a preferred filmthickness range of 0.5-1 μm to form first isolation dielectric 45 asshown in FIG. 7i. A second isolation dielectric layer 46 of electricallyinsulating material is deposited over first isolation dielectric layer45 to a preferred thickness of 200 nm as shown in FIG. 7j. The preferredmaterial for dielectric layer 46 is silicon dioxide deposited by aplasma enhanced chemical vapor deposition (“PECVD”) process.

[0110]FIGS. 8a-8 m (collectively “FIG. 8”) illustrate further steps inaccordance with the invention for manufacturing the light modulator ofFIG. 1 starting with the intermediate structure fabricated according tothe steps of FIG. 7. FIG. 8 presents a preferred sequence forfabrication of the TFT array. A layer of amorphous silicon (α-Si) 47 isdeposited by conventional PECVD means from a gaseous mix of silane andhelium to a preferred thickness of 90 nm as shown in FIG. 8a. Blanketlayer 47 is then made conductive to contact with metals formingsilicides. A preferred metal is chromium. Referring to FIG. 8b, siliconlayer 47 is made electrically conductive n-type by bombarding it withphosphorus ions at an energy of 30 kV and a high dosage of 4×10¹⁵ions/cm².

[0111] As shown in FIG. 8c, heavily doped n-type silicon layer 47 iscoated with a positive tone photoresist 100 and exposed to actinic lightthrough a photomask, with alignment and optical registration tosuperimpose pattern 105 to the previously defined array of displayelectrodes 31, and subsequently developed by conventional means todefine pattern 105 in the resist whereby portions of amorphous siliconlayer 47 are uncovered. The uncovered portions of silicon layer 47 areetched by conventional reactive ion etching (“RIE”) in a gas containingfluoride ions to define an array of heavily doped n-type source/drainpairs 48 as shown in FIG. 8d. A preferred etching gas is sulfurhexafluoride (SF₆). Each source/drain pair 48 is associated with, andoverlies, a display electrode location. In each source/drain pair, afirst region 51, associated with a source electrode, and a second region52, associated with a drain electrode, are spaced apart by a distancedetermined by the requirements for TFT channel geometry. In the presentinvention, the channel length is 2 μm, and the channel width is 3 μm.Additionally, each source/drain region 51 or 52 is comprised of a firstcontact area CA1 and a second contact area CA2. Contact area CA1constitutes approximately half of the area of region 51 or 52. Contactarea CA2 constitutes the remaining half.

[0112] As shown in FIG. 8e, second dielectric layer 46, together withsource/drain pair array 48, is coated with a positive tone photoresist100 and exposed to actinic light through a photomask, with alignment andoptical registration to superimpose source via pattern 106 to thepreviously defined display electrode array, and subsequently developedby conventional means to define pattern 106 in resist 100 wherebyportions of second dielectric isolation layer 46 are uncovered. Theexposed material of layer 46 is etched by conventional RIE gas chemistrycontaining fluoride ions to expose portions of first isolationdielectric layer 45. A preferred RIE gas composition is sulfurhexafluoride. Isolation dielectric layer 45, together with storagecapacitor dielectric layer 41, is dry etched by conventional oxygenplasma gas chemistry to form source vias 49. Display electrodes 31 arenot etched by the chemistry used to etch source vias 49, and so providesa stop for the etching process. Vias 49 are subsequently etched by wetchemistry containing fluoride ions to remove residues from the dry etchprocess and to etch back second isolation dielectric layer 46 toincrease the via dimension in layer 46 as shown in FIG. 8f to a largerdimension than source vias 49 in layer 45.

[0113] A blanket layer of metal 50 forming ohmic contact to n+source/drain pair array 48 is deposited by sputtering means over secondisolation dielectric layer 46, source/drain pair array 48 and intosource vias 49, contacting the exposed portions of display electrodes31. A preferred metal is chromium deposited to a thickness of 200 nm. Asshown in FIG. 8g, metal layer 50 is coated with a positive tonephotoresist 100 and exposed to actinic light through a photomask, withalignment and optical registration to superimpose pattern 107 overpreviously defined source/drain pairs 48, and subsequently developed byconventional means to define pattern 107 in resist 100 whereby portionsof metal layer 50 are uncovered. The uncovered portions of layer 50 arechemically etched with a commercially available etchant provided byTransene Chemicals or other vendor to remove the metal in the regionsdefined by pattern 107 to define source-electrode pattern 53 anddrain-electrode pattern 54. Each source electrode 53 overlies a sourcevia 49, making electrical contact to a display electrode 31, and anassociated contact area CA1 of a source region 51 as shown in FIG. 8h.Each drain electrode 54 is electrically connected in common to all otherdrain electrodes 54 and makes electrical contact to associated contactarea CA1 of a drain region 52.

[0114] A semiconductor layer 55 of amorphous silicon (α-Si) is depositedby conventional PECVD means from a gaseous mix of silane and helium to apreferred thickness of 90 nm so as to overlie source/drain pair array48, source electrodes 53, drain electrodes 54, and second isolationdielectric 46. A gate dielectric layer 56 of silicon nitride isdeposited by PECVD from a gas mix of silane and ammonia over siliconlayer 55. Layers 55 and 56 are preferably deposited sequentially fromthe same deposition tool without exposure of amorphous silicon layer 55to atmospheric contamination. Gate dielectric layer 56 is coated with apositive tone photoresist 100 and exposed to actinic light through aphotomask, with alignment and optical registration to superimposepattern 108 over previously defined source/drain pair array 48, andsubsequently developed by conventional means to define pattern 108 inresist 100 whereby portions of gate dielectric layer 56 are uncovered.The exposed portions of gate dielectric layer 56 and silicon layer 55are sequentially dry etched by conventional RIE means using sulfurhexafluoride gas chemistry to define silicon islands 57 together withoverlying gate dielectric layers 58. Source electrodes 53 and drainelectrode 54 are not etched by this chemistry, and so provide etchstopping. Each silicon island 57 overlies the contact area CA2 of asource region 51 and contact area CA2 of associated drain region 52 asshown in FIG. 8i.

[0115] Referring to FIG. 8j, a blanket layer 59 of electricallyinsulating material with the materials property of a high ratio ofemitted secondary electrons when stimulated by a primary electron beamof sufficient energy is deposited to a thickness of 10 nm over theuncovered portions of gate dielectric layers 58, source electrodes 53,drain electrodes 54, and second isolation dielectric 56. A preferredmaterial for delta layer 59 is magnesium oxide deposited by vacuumevaporation.

[0116] As shown in FIG. 8k, delta layer 59 is coated with a liquidpolymer material, such as P12610 supplied by HD Microsystems, and curedat 350° C. to a preferred film thickness of 1-1.5 μm to form anelectrically insulating layer 60. A blanket layer 61 of chromium issputter deposited over delta layer 59 to a preferred thickness of 300nm. As shown in FIG. 8l, chromium layer 61 is coated with a positivetone photoresist 100 and exposed to actinic light through a photomask,with alignment and optical registration to superimpose pattern 109 overpreviously defined gate dielectric layer 58, and subsequently developedby conventional means to define pattern 109 in resist 100 wherebyportions of chromium layer 61 are uncovered. The uncovered chromium ischemically etched in a commercially available etchant provided byTransene Chemicals or other vendor to remove chromium metal in theregions defined by pattern 109 to define collector grid 62, and toexpose portions of insulating layer 60 in regions overlying gatedielectric 58. The exposed regions of layer 60 are etched by RIE, usingoxygen plus fluoride ion gas chemistry, to remove the portions ofpolymeric insulating layer 60 in the regions not protected by collectorelectrode 62 to form collector insulator 63 as shown in FIG. 8m.Chromium has high selectivity to the etchant chemistry, and so providesa suitable etch mask for removal of polymer. Additionally, delta layer59 is not attacked by this etchant chemistry, and so serves an etch stopto protect gate dielectric 58 from damage. TFTs 204 of active matrix 201are now complete.

[0117] In order to construct a liquid-crystal spatial light modulator,display electrodes 31 and spacing elements 43 must be released frommandrel substrate 20. FIGS. 9a-9 d (collectively “FIG. 9”) illustratesteps in accordance with the invention for removing mandrel substrate 20in manufacturing the light modulator of FIG. 1. To improve handlingproperties during release, and provide a robust backing for the arrayduring subsequent liquid-crystal cell processing, a sacrificial backingfilm is created. As shown in FIG. 9a, a layer of dry film photoresist101 is laminated to TFT array 201, making contact only to collector grid62, to a form sub-assembly 110. A preferred dry film photoresist isRiston Tentmaster dry film tenting resist formulated to span the spacebetween features similar to collector grid 62. Resist 101 is laminatedto collector grid 62 by a heated roller process at 105° C., followingarray processing. Riston is a negative tone photoresist, withpolymerization in areas exposed to actinic light. In this case whereRiston is used as a sacrificial film and must be subsequently removed,resist 101 is not exposed to actinic light in order to facilitatestripping of the protective Riston film material following the cellfabrication process.

[0118] A single edge termination of laminated resist 101, overlyingcompleted array 201 and including mandrel 20, is attached by an adhesivefilm strip 151 to a delamination roller 150 as shown in FIG. 9b. Roller150, with rotation as shown in FIG. 9b, produces delamination ofsubassembly 110 from mandrel 20. The delamination of subassembly 110from mandrel 20 takes place at the surface of mandrel 20 coated withmold release 22 to reveal lower modulator surface 701 formed withspacing elements 43 and display electrodes 31 as shown in FIG. 9c.

[0119] In order to obtain good optical characteristics, liquid-crystalcells 202 must possess ordered alignment of their liquid-crystalmolecules. This is typically accomplished by depositing a thindielectric layer (not shown) over common electrode 91 and array surface701. A preferred material is silicon oxide deposited over displayelectrodes 31 and associated spacer elements 43 to a thickness of 20 nmby vacuum evaporation means to form an alignment surface as shown inFIG. 9d.

[0120]FIGS. 10-13 illustrate the remaining steps in accordance with theinvention for manufacturing the light modulator of FIG. 1. Referring toFIG. 10, thermoplastic resin seal material, such as UVG-21 supplied byCardinal Industries, is dispensed over common electrode 91 in a patterncorresponding to the perimeter of subassembly 110 to form a perimeterseal ring 710. The width of perimeter seal 710 is 0.25-0.5 mm. A gap711, typically 3-5 mm, in the perimeter seal pattern facilitatessubsequent filling of the liquid-crystal material following cellassembly. A first cure of seal ring 710 is obtained by exposure of theuncured ring to actinic light at a wavelength of 240-365 nm.

[0121] Subassembly 110 is bonded to common electrode 91 by firstoverlaying subassembly 110 onto perimeter seal ring 710 at a temperatureof 150° C. and then applying sufficient pressure to backing resist 101and substrate 90 to create a hermetic seal at seal ring 710 as shown inFIG. 11.

[0122] The liquid-crystal material for liquid-crystal cells 202 isintroduced into cavity formed by subassembly 110 and electrode 91 by wayof seal ring gap 711 as shown in FIG. 12. After filling, sufficientpressure is applied to backing resist to remove excess liquid-crystalmaterial by expelling through gap 711. Flexible subassembly 110 conformsto the contour of electrode 91 overlying substrate 90 so that spacingelements 43 make contact to electrode 91 as shown in FIG. 13. Gap 711 issealed by conventional means using UV-cured adhesive supplied by NorlandProducts.

[0123] Resist 101, which has not been exposed to actinic light, isremoved by spray developing in a Riston developer. Liquid-crystal cells202 are hermetically sealed in a cavity 71 and are protected from thespray developing solution. Exposed features 59, 62, and 63 are also notaffected by spray developing.

[0124] Referring to FIG. 14, liquid-crystal cells 202, active matrix201, and flexible membrane 200, spaced away from electrode 91 overlyingtransparent substrate 90, together with electron-beam guns 400 and 500,packaged in a suitable vacuum envelope 901, form anelectron-beam-addressed spatial light modulator 900.

[0125] White light constituted with light wavelengths in the visiblespectrum, emitted from a lamp 902, is separated into wavelengthpassbands comprising the primary color (red, blue, and green) spectrum.A primary color passband is polarized into a first polarization state912 and a second polarization state 910 by means of a polarization beamsplitter 903 supplied by Optical Coating Laboratories Incorporated(“OCLI”). Light of a first polarization state 912 is directed to thearray of reflective display electrodes 31 by transmission throughtransparent substrate 90, common electrode 91, and liquid-crystal cells202. The liquid-crystal molecules are aligned by the alignment coatingso as to transmit light of first polarization state 912 when displayelectrodes 31 are equipotential with common electrodes 91. Light offirst polarization state 912 is reflected from display electrodes 31,and directed to polarizing beam splitter 903 whereby it is reflectedaway from a projection lens 904, and no image is projected to a viewingscreen 905.

[0126] Image information generated by a video source is represented as apattern of electron beam-induced charges on gate delta coatings 59overlying active matrix 201. TFT current charges the array of displayelectrodes 31 to voltages corresponding to the charge pattern on the TFTarray. The potential differences between display electrodes 31 andcommon electrode 91 result in electric field-induced rotation of theliquid-crystal molecules so as to align to the field direction. Themaximum electric field results in molecular orientation orthogonal tothe zero-field orientation, whereby light of first polarization state912 is rotated relative to second polarization state 910. Light ofsecond polarization state 910 is reflected from display electrodes 31,and relayed to beam splitter 903, whereby it is transmitted toprojection lens 904 and projected onto viewing screen 905 as an image ofmaximum brightness.

[0127] An electric field across a liquid-crystal cell 202 ofintermediate strength, between minimum and maximum, results in molecularrotation intermediate between orthogonal orientations to provide animage portion of intermediate brightness transmitted to viewing screen905.

[0128] Full color image projection is typically obtained by combiningthree spatial light modulators into a projection engine 906 as shown inFIG. 15, whereby primary color projection light from each polarizationbeam splitter 903 is combined by a color combiner 907, supplied by OCLI,prior to projection lens 904.

[0129] While the invention has been described with reference toparticular embodiments, this description is solely for the purpose ofillustration and is not be construed as limiting the scope of theinvention claimed below. For instance, liquid-crystal cells 202 may beformed with liquid crystal having different properties than thatdescribed above. Devices such as flat-panel emission arrays orphotocathodes may be used in place of an electron-beam system to depositelectrical charge on active matrix 201. The light modulator of FIG. 1can be used in a digital mode.

[0130] Each TFT 204 can be replaced with a floating-gate TFT configuredthe same as TFTs 204 except that a floating-gate electrode is situatedbetween gate dielectric layer 58 and delta coating 59 above thesemiconductor material between source/drain regions 51 and 52. Thefloating-gate electrode typically consists of electrically conductiveor/and resistive material. Alternatively, delta coating 59 in thefloating-gate TFT can be replaced with a dielectric layer which does notsignificantly emit secondary electrons, i.e., whose secondary electronemission coefficient δ is less than 1 for all values of average primaryelectron energy V_(PE).

[0131] The present light modulator can be fabricated using compatiblematerials and manufacturing techniques other than those described above.Light passbands outside the visible passband can be modulated inaccordance with the invention. Various modifications and applicationsmay thus be made by those skilled in the art without departing form thetrue scope of the invention as defined in the appended claims.

We claim:
 1. A structure comprising: a substrate; a plurality of liquid-crystal cells overlying the substrate above where the substrate is substantially transmissive of specified light; a like plurality of transistors respectively corresponding to the liquid-crystal cells, each transistor being in electrical communication with the corresponding liquid-crystal cell; an electron-beam system for bombarding each transistor with electrons that cause it to be selectively in (i) a non-conductive condition in which its channel-region electric field is substantially insufficient for conduction or (ii) a conductive condition in which its channel-region electric field is sufficient for at least partial conduction; and a control component which, during selected time periods when a transistor is in its conductive condition, provides that transistor with a control signal that results in the specified light having its polarization direction selectively rotated in the corresponding liquid-crystal cell.
 2. A structure as in claim 1 wherein, during disablement periods, the control component causes all the transistors to be disabled regardless of whether each transistor is in its conductive or non-conductive condition.
 3. A structure as in claim 1 wherein each liquid-crystal cell operates from (i) a low-rotation condition in which the polarization direction of the specified light in that cell rotates a first amount as little as zero to (ii) a high-rotation condition in which the polarization direction of the specified light in that cell rotates a second amount greater than the first amount.
 4. A structure as in claim 3 wherein the transistors are electrically coupled together for receiving their control signals as substantially a common control signal from the control component.
 5. A structure as in claim 4 wherein the common control signal is largely at (a) one of at least one low-impedance erase value that results in all the liquid-crystal cells being in their low-rotation conditions, (b) one of at least one low-impedance writing value that results in the polarization direction of the specified light being selectively rotated in each liquid-crystal cell for which the corresponding transistor is in its conductive condition, or (c) one of at least one high-impedance value that causes all the transistors to be disabled regardless of whether each transistor is in its conductive or non-conductive condition.
 6. A structure as in claim 5 wherein one erase value of the common control signal lies approximately midway between two writing values of the common control signal, the control component alternating between the two writing values in generating the common control signal.
 7. A structure as in claim 1 wherein the electron-beam system generates a scanning electron beam for selectively bombarding each transistor with electrons at a dosage and average energy which cause that transistor to be in its conductive condition.
 8. A structure as in claim 7 wherein electrons provided by the scanning electron beam selectively cause each bombarded transistor to become electrically charged to at least a threshold level and thereby placed in that transistor's conductive condition.
 9. A structure as in claim 8 wherein each transistor is in its conductive condition when it is positively charged.
 10. A structure as in claim 7 wherein electrons of the scanning electron beam bombard selected ones of the transistors in accordance with an image pattern while all of the transistors are disabled.
 11. A structure as in claim 10 wherein the electron-beam system modulates the current of the scanning electron beam in accordance with image gray levels for causing the conductive condition of each transistor to vary between a low-field condition and a high-field condition such that the polarization direction of the specified light in the corresponding liquid-crystal cell is rotated in a corresponding manner.
 12. A structure as in claim 7 wherein the electron-beam system generates an additional electron beam for largely simultaneously bombarding all the transistors during selected bombardment time periods with electrons at a dose and average energy which cause all the transistors to be in their conductive conditions.
 13. A structure as in claim 12 wherein electrons of the additional electron beam simultaneously bombard all of the transistors during other bombardment time periods with electrons at a dosage and average energy which cause all of the transistors to be in their non-conductive conditions.
 14. A structure as in claim 13 wherein the average electron energy is greater during bombardment of the transistors for causing them to be in their conductive conditions than for causing them to be in their non-conductive conditions.
 15. A structure as in claim 7 wherein the electron-beam system generates an additional electron beam for largely simultaneously bombarding selected ones of the transistors during selected bombardment time periods with electrons at a dose and average energy which cause each selected transistor to be in its non-conductive condition.
 16. A structure as in claim 1 further including a flexible membrane situated between each transistor and the corresponding liquid-crystal cell.
 17. A structure as in claim 17 wherein the membrane includes spacing elements situated between the liquid-crystal cells.
 18. A structure as in claim 16 wherein the transistors electrically communicate with the liquid-crystal cells through openings in the membrane.
 19. A structure as in claim 1 wherein each transistor comprises: first and second laterally separated source/drain regions, the first source/drain region being in electrical communication with the liquid-crystal cell corresponding to that transistor; a semiconductor layer having semiconductor material that extends between the source/drain regions; and a gate element situated above at least the semiconductor material between the source/drain regions for controlling the conductive and non-conductive conditions of that transistor.
 20. A structure as in claim 19 wherein, upon being bombarded by electrons at a dosage and average energy suitable for causing the transistors to be in their conductive conditions, the gate element of each transistor is sufficiently electrically charged in a selected charging direction to induce the channel-region electric field for that transistor's conductive condition.
 21. A structure as in claim 20 wherein, upon being bombarded by electrons at a dosage and average energy suitable for causing the transistors to be in their non-conductive conditions, the gate element of each transistor electrically charges sufficiently in a further charging direction opposite to the selected charging direction to induce the channel-region electric field for that transistor's non-conductive condition.
 22. A structure as in claim 19 wherein the gate element of each transistor has an exposed surface which is bombarded by electrons from the electron-beam system and which has a secondary emission coefficient (a) less than 1 when electrons bombard that surface at an average energy below a crossover value and (b) greater than 1 when electrons bombard that surface at an average energy above the crossover value in a range extending to a higher energy value.
 23. A structure as in claim 19 wherein the gate element of each transistor comprises: a first gate dielectric layer situated over at least the semiconductor material between the source/drain regions; and a second gate dielectric layer overlying the first gate dielectric layer, the second gate dielectric layer being capable of storing electrical charge and of having its electrical charge change upon being bombarded by electrons from the electron-beam system so as to selectively induce the channel-region electric field for the non-conductive or conductive condition of that transistor depending on the electron dose and average energy.
 24. A structure as in claim 23 wherein the second gate dielectric layer of each transistor has a secondary electron emission coefficient (a) less than 1 when electrons bombard the second gate dielectric layer at an average energy below a crossover value and (b) greater than 1 when electrons bombard the second gate dielectric layer at an average energy above the crossover value in a range extending to a higher energy value.
 25. A structure as in claim 19 further including a like plurality of display electrodes respectively corresponding to the liquid-crystal cells and thereby respectively corresponding to the transistors, each display electrode electrically coupled to the first source/drain region of the corresponding transistor and electrically contacting the corresponding liquid-crystal cell along largely all of its upper surface.
 26. A structure as in claim 25 wherein each display electrode is light reflective along where it contacts the upper surface of the corresponding liquid-crystal cell.
 27. A structure as in claim 1 wherein: the structure is allocated into an array of pixels, each comprising multiple subpixels, the subpixels having an average subpixel width in a first lateral direction; the electron-beam system generates an electron beam for scanning the subpixels, the electron beam having a beam width in the first lateral direction as the electron scans the subpixels in a second lateral direction generally perpendicular to the first lateral direction, the beam width in the first lateral direction being substantially at least twice the average subpixel width in the first lateral direction.
 28. A structure as in claim 27 wherein: each subpixel comprises one of the transistors and the corresponding one of the liquid-crystal cells: and the transistor have, in the first lateral direction, an average transistor width largely constituting the average subpixel width in the first lateral direction.
 29. A structure as in claim 1 wherein the specified light comprises visible light.
 30. A structure as in claim 29 wherein the visible light comprises color light.
 31. A method of operating a light-modulating structure in which (a) a plurality of liquid-crystal cells overlie a substrate above where the substrate is substantially transmissive of specified light, (b) each of a like plurality of transistors respectively corresponding to the liquid-crystal cells is in (b1) a non-conductive condition in which its channel-region electric field is substantially insufficient for conduction or (b2) a conductive condition in which its channel-region electric field is sufficient for at least partial conduction, and (c) each transistor is in electrical communication with the corresponding liquid-crystal cell, the method being initiated with all the transistors in their non-conductive conditions, the method comprising: sequentially bombarding selected ones of the transistors with electrons according to an image pattern at a dosage and average energy that cause each selected transistor to enter its conductive condition while all the transistors are disabled; and subsequently enabling each selected transistor in a writing manner that results in the specified light having its polarization direction selectively rotated in the corresponding liquid-crystal cell where, when there are multiple selected transistors, all of the selected transistors are so enabled substantially simultaneously so as to result in the specified light having its polarization directions selectively rotated substantially simultaneously in all of the corresponding liquid-crystal cells.
 32. A method as in claim 31 further including subsequent to the enabling act: substantially simultaneously bombarding all the transistors with electrons at a dosage and average energy that cause all the transistors to be in their conductive conditions while being enabled in an erasing manner that results in the polarization directions of the specified light in all the liquid-crystal cells being rotated substantially the same amount as little as zero; and subsequently substantially simultaneously bombarding all the transistors with electrons at a dosage and average energy that cause all the transistors to enter their non-conductive conditions while all the transistors are disabled.
 33. A method as in claim 32 further including, subsequent to the enabling act and prior to the second-occurring bombarding act, bombarding each selected transistor with electrons at a dosage and average energy that cause that transistor to return to its non-conductive condition while all the transistors are disabled where, when there are multiple selected transistors, all of the selected transistors are so bombarded substantially simultaneously.
 34. A method as in claim 32 wherein the average energy of the electrons is higher for each of the first-occurring and second-occurring bombarding acts than for the third-occurring bombarding act.
 35. A method as in claim 29 wherein: the light-modulating structure is allocated into an array of pixels, each comprising multiple subpixels, each subpixel comprising one of the transistors and the corresponding one of the liquid-crystal cells, the transistor having an average transistor width in a first lateral direction; and the bombarding act comprises bombarding the transistors with electrons of a scanning electron beam whose beam width in the first lateral direction is, as the electron beam scans the transistors in a second lateral direction generally perpendicular to the first lateral direction, substantially at least twice the average transistor width in the first lateral direction.
 36. A method as in claim 35 wherein the electron beam provides electrons having a generally Gaussian spatial distribution in the first lateral direction, the beam width in the first lateral direction being the Gaussian distribution width at which the current density of the electron beam is one half the maximum current density of the electron beam.
 37. A method of operating a light-modulating structure in which (a) a plurality of liquid-crystal cells overlie a substrate above where the substrate is substantially transmissive of specified light, (b) each of a like plurality of transistors respectively corresponding to the liquid-crystal cells is in (b1) a non-conductive condition in which its channel-region electric field is substantially insufficient for conduction or (b2) a conductive condition in which its channel-region electric field is sufficient for at least partial conduction, and (c) each transistor comprises (c1) first and second laterally separated source/drain regions with the first source/drain region being in electrical communication with the liquid-crystal cell corresponding to that transistor, (c2) a semiconductor layer having semiconductor material that extends between the source/drain regions, and (c3) a gate element situated at least partially above the semiconductor material between the source/drain regions for controlling the conductive and non-conductive conditions of that transistor, the method being initiated with all the transistors in their non-conductive conditions, the method comprising: sequentially bombarding the gate elements of selected ones of the transistors with electrons according to an image pattern at a dosage and average energy that cause each selected transistor to enter its conductive condition while the second source/drain regions of all the transistors are electrically subjected to transistor-disabling high impedance; and subsequently providing the second source/drain regions of all the transistors with a low-impedance writing voltage that results in the specified light having its polarization direction selectively rotated in the liquid-crystal cell corresponding to each selected transistor where, when there are multiple selected transistors, the second source/drain regions of all the selected transistors receive the low-impedance writing voltage substantially simultaneously so as to result in the specified light having its polarization directions selectively rotated substantially simultaneously in all of the corresponding liquid-crystal cells.
 38. A method as in claim 37 further including subsequent to the providing act: substantially simultaneously bombarding the gate elements of all the transistors with electrons at a dosage and average energy that cause all the transistors to be in their conductive conditions while the second source/drain regions of all the transistors are provided with a low-impedance erase voltage that results in the polarization directions of the specified light in all the liquid-crystal cells being rotated substantially the same amount as little as zero; and subsequently substantially simultaneously bombarding the gate elements of all the transistors with electrons at a dosage and average energy that cause all the transistors to enter their non-conductive conditions while the second source/drain regions of all the transistors are electrically subjected to transistor-disabling high impedance.
 39. A method as in claim 38 further including, subsequent to the providing act and prior to the second-occurring bombarding act, bombarding the gate element of each selected transistor with electrons at a dosage and average energy that cause that transistor to return to its non-conductive condition while the second source/drain regions of all the transistors are electrically subjected to transistor-disabling high impedance where, when there are multiple selected transistors, the gate elements of all the selected transistors are so bombarded substantially simultaneously.
 40. A method as in claim 38 wherein the average energy of the electrons is higher for each of the first-occurring and second-occurring bombarding acts than for the third-occurring bombarding act.
 41. A method as in claim 38 further including repeating the bombarding and providing acts with potentially a different image pattern wherein: the erase voltage is at largely the same erase value during both bombarding acts in which the erase voltage is provided; the writing voltage is a largely one writing value during one of the providing acts and at largely another writing value during the other of the providing acts; and the erase value lies approximately midway between the two writing values.
 42. A method as in claim 37 wherein each liquid-crystal cell operates from (i) a low-rotation condition in which the polarization direction of the specified light in that cell rotates a first amount as little as zero to (ii) a high-rotation condition in which the polarization direction of the specified light in that cell rotates a second amount greater than the first amount.
 43. A method as in claim 37 wherein the second source/drain regions of all the transistors are electrically coupled together to a control component.
 44. A method as in claim 37 wherein the light-modulating structure further including a flexible membrane situated between each transistor and the corresponding liquid-crystal cell.
 45. A method as in claim 37 wherein the gate element of each transistor comprises: a first gate dielectric layer situated over at least the semiconductor material between the source/drain regions; and a second gate dielectric layer overlying the first gate dielectric layer, the second gate dielectric layer being capable of storing electrical charge and of having its electrical charge change upon being bombarded by electrons so as to selectively induce the channel-region electric field for the non-conductive or conductive condition of that transistor depending on the electron dose and average energy.
 46. A method as in claim 37 wherein the light-modulating structure further including a like plurality of display electrodes respectively corresponding to the liquid-crystal cells and thereby respectively corresponding to the transistors, each display electrode electrically coupled to the first source/drain region of the corresponding transistor and electrically contacting the corresponding liquid-crystal cell along largely all of its upper surface.
 47. A method as in claim 45 wherein each display electrode contacts the corresponding liquid-crystal cell along its upper surface, the specified light being reflected off each display electrode along where it meets the upper surface of the corresponding liquid-crystal cell.
 48. A method as in claim 47 wherein the light-modulating structure further includes: an electron-beam system for bombarding the gate elements of the transistors with electrons; and a control component for disabling the transistors and for providing the writing and erase voltages.
 49. A method comprising: fabricating a light-modulating structure in which (a) a plurality of liquid-crystal cells overlie a structure substrate above where the structure substrate is substantially transmissive of specified light and (b) each of a like plurality of transistors respectively corresponding to the liquid-crystal cells is in electrical communication with the corresponding liquid-crystal cell; providing an electron-beam system for bombarding each transistor with electrons that cause it to be selectively in (i) a non-conductive condition in which its channel-region electric field is substantially insufficient for conduction or (ii) a conductive condition in which its channel-region electric field is sufficient for at least partial conduction; and providing a control component which, during selected time periods when a transistor is in its conductive condition, provides that transistor with a control signal that results in the specified light having its polarization direction selectively rotated in the corresponding liquid-crystal cell.
 50. A method as in claim 49 wherein the fabricating act includes electrically coupling the transistors together for receiving their control signals as substantially a common control signal from the control component.
 51. A method as in claim 49 wherein the fabricating act includes furnishing the light-modulation structure with a flexible membrane situated between each transistor and the corresponding liquid-crystal cell.
 52. A method as in claim 49 wherein the fabricating act includes creating each transistor-to comprise: first and second laterally separated source/drain regions with the first source/drain region being in electrical communication with the liquid-crystal cell corresponding to that transistor; a semiconductor layer having semiconductor material that extends between the source/drain regions; and a gate element situated above at least the semiconductor material between the source/drain regions for controlling the conductive and non-conductive conditions of that transistor.
 53. A method as in claim 52 wherein an exposed surface of the gate element of each transistor has a secondary electron emission coefficient (a) less than 1 for electron bombardment at an average energy below a crossover value and (b) greater than for electron bombardment at an average energy above a crossover value in a range extending to a higher energy value.
 54. A method as in claim 52 wherein the creating acts comprises forming the gate element of each transistor to comprise: a first gate dielectric layer situated over at least the semiconductor material between the source/drain regions; and a second gate dielectric layer overlying the first gate dielectric layer, the second gate dielectric layer being capable of storing electrical charge and of having its electrical charge change upon being bombarded by electrons from the electron-beam system so as to selectively induce the channel-region electric field for the non-conductive or conductive condition of that transistor depending on the electron dose and average energy.
 55. A method as in claim 54 wherein the second gate dielectric layer of each transistor has a secondary electron emission coefficient (a) less than 1 for electron bombardment at an average energy below a crossover value and (b) greater than for electron bombardment at an average energy above a crossover value in a range extending to a higher energy value.
 56. A method as in claim 52 wherein the fabricating act includes furnishing the light-modulation structure with a like plurality of display electrodes respectively corresponding to the liquid-crystal cells and thereby respectively corresponding to the transistors such that each display electrode is electrically coupled to the first source/drain region of the corresponding transistor and electrically contacts the corresponding liquid-crystal cell along largely all of its upper surface.
 57. A method as in claim 56 wherein each display electrode is light reflective along where it contacts the upper surface of the corresponding liquid-crystal cell.
 58. A method as in claim 49 wherein the fabricating act includes: forming, on a mandrel substrate, an intermediate structure having a like plurality of bottom-side depressions at respective locations for the liquid-crystal cells; forming the transistors on the intermediate structure; removing the mandrel substrate; substantially removing any material in the bottom-side depressions; substantially filling the bottom-side depressions with liquid-crystal material; and providing the structure substrate below the depressions as substantially filled with the liquid-crystal cell material. 